1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a defective memory cell address detecting circuit used in a semiconductor memory so configured to be recovered by replacing a defective memory cell with a redundant memory cell.
2. Description of Related Art
In the prior art, in many cases, this type of semiconductor memory has such a redundant construction that, when a defective memory cell exists in a memory cell array in which data is written and read in accordance with an address designated by an address signal supplied from an external, the defective memory cell is replaced with a previously prepared redundant memory cell, so that the whole of the chip is saved from a small amount of defective memory cells. In this case, there is provided a defective memory cell address detecting circuit for discriminating whether or not a given address is the address of the defective memory cell. This type of semiconductor memory having the redundant memory cell array in addition to the memory cell array is disclosed in, for example, U.S. Pat. No. 5,586,075 and European Patent EP 0 763 794 A2, the content of both of which is incorporated by reference in its entirety into this application.
Referring to FIG. 5, there is shown a circuit diagram for illustrating one example of the prior art defective memory cell address detecting circuit.
As shown in FIG. 5, the shown prior art example includes fuses f1, f3, f5 and f7 having one end receiving address bits A0T, A1T, A2T and A3T of an address signal, respectively, inverters Inv1, Inv2, Inv3 and Inv4 receiving the address bits A0T, A1T, A2T and A3T, respectively, for outputting inverted address bits A0N, A1N, A2N and A3N, respectively, fuses f2, f4, f6 and f8 having one end receiving the inverted address bits A0N, A1N, A2N and A3N, respectively, and source-grounded MOS transistors Tr1 to Tr8 having a gate connected to the other end of the fuses f1 to f8, respectively, so that at least one of these MOS transistors is turned on when an address other than the address of the defective memory cell is inputted. The shown circuit also includes a MOS transistor Tr18 having a drain connected to a power supply voltage, a gate connected to receive a precharge signal P, and a source connected to a drain of each of the MOS transistors Tr1 to Tr8, for precharging a signal line LCOMP for outputting a signal indicative of the result of the defective memory cell address detection. This signal will be called a "COMP signal" in this specification.
With this arrangement, in the case that a defective memory cell exists in the memory cell array, there are cut off only ones so selected from the fuses f1 to f8 as to maintain all of the MOS transistors Tr1 to Tr8 in an OFF condition only when an external address indicates the address of the defective memory cell. For example, assuming that the memory cell at the address (A0T, A1T, A2T, A3T)=(0, 1, 1, 0) is defective, if the fuses f2, f3, f5 and f8 are cut off, all the MOS transistors Tr1 to Tr8 are maintained in the OFF condition only when the external address indicates the address of the defective memory cell, and any one of the MOS transistors Tr1 to Tr8 is turned on when the external address indicates an address other than the address of the defective memory cell.
Now, an operation of the defective memory cell address detecting circuit constructed as mentioned above will be described.
First, the MOS transistor Tr18 is put in an ON condition during a predetermined period of time by the precharge signal P supplied from an external. Thus, the signal line LCOMP for the COMP signal is precharged to a high level. On the other hand, the defective address detection is carried out after completion of this precharging.
When the external address indicates an address of a non-defective memory cell in the memory cell array, since any one of the MOS transistors Tr1 to Tr8 is turned on, the signal line LCOMP for the COMP signal is brought to a low level.
However, when the external address indicates the address of the defective memory cell in the memory cell array, since all of the MOS transistors Tr1 to Tr8 are maintained in the OFF condition, the signal line LCOMP for the COMP signal is maintained at the high level.
When the COMP signal is at the low level, the memory cell array is maintained in an operating condition, and on the other hand, the redundant memory cell is maintained in a non-operating condition. When the COMP signal is at the high level, the memory cell array is put in the non-operating condition, and on the other hand, the redundant memory cell is put in the operating condition.
As mentioned above, even if the defective memory cell exists in the memory cell array, the whole of the chip can be recovered by replacing the defective memory cell with a previously prepared redundant memory cell.
In the above mentioned prior art defective memory cell address detecting circuit, the MOS transistor for receiving the address signal and the MOS transistor receiving the inverted signal of the address signal are provided independently for each bit of the address, and fuses are cut off which are selected from among the fuses connected to the MOS transistors so as to maintain all the MOS transistors in the OFF condition only when the external address signal designates the address of the defective memory cell. Accordingly, the transistors connected to the cut-off fuses become unnecessary for detecting the address of the defective memory address.
Here, if the number of unnecessary transistors becomes large, a load capacitance of the signal line LCOMP for the COMP signal indicative of the result of the defective memory cell address detection becomes large, with the result that a significant signal delay occurs.